As technology nodes shrink, in some IC designs, there has been a desire to replace the traditional polysilicon gate electrode with a metal gate electrode to improve device performance with the decreased feature sizes. Providing metal gate structures (e.g., including a metal gate electrode rather than polysilicon) offers one solution. One process of forming a metal gate stack is termed a “gate last” process in which the final gate stack is fabricated “last” which allows for a reduced number of subsequent processes, including high temperature processing, that are performed before formation of the gate stack. Additionally, as the dimensions of transistors decrease, the thickness of the gate oxide may be reduced to maintain performance with the decreased gate length. In order to reduce gate leakage, high dielectric constant (high-k or HK) gate insulator layers are also used which allows to maintain the same effective thickness as would be provided by a typical gate oxide used in larger technology nodes.
However, when a high k dielectric material and a metal are adopted to form a gate stack, various issues may arise when integrating the processes and materials for this purpose. For example, device reliability issues may be induced by properties of a barrier layer (sometimes referred to as a “cap layer”) between a high k dielectric material and a metal. In another example, it can be challenging to tune the work functions for NMOS transistor and PMOS transistors independently and properly.